1. Field of the Invention
The invention relates to a collector-up heterojunction bipolar transistor and its method of production.
The invention aims to enhance electron transport in heterojunction bipolar transistors (HBT) in collector-up topology, while ensuring a high production yield.
2. Description of the Background
The collector-up configuration is particularly beneficial in the case of a heterojunction bipolar transistor because of the low values of base-collector capacitance which it makes it possible to obtain by comparison with those encountered with a conventional topology, called emitter-up topology. The reduction in this junction capacitance especially makes it possible to enhance the UHF performance of this type of component.
In contrast, if a few specific precautions are not taken, parasitic injection of electrons into the extrinsic base areas appears in an HBT. These electrons are then picked up by the base contacts or recombine in the extrinsic base; which, in both cases, leads to a degradation of the transport factor in the base and thus heavily penalizes the current gain of the transistor. Certain solutions have already been applied to this problem, and especially in the case of collector-up HBTs fabricated with GaAlAs/GaAs or GaInP/GAs materials.
Thus Yamahata et al. describe, in a publication (IEEE Electron Device Letters, Vol. 14, No 4, April 1993) a GaAlAs/GaAs collector-up single heterojunction bipolar transistor (S-HBT) in which the emitter region situated above the extrinsic base is converted into a highly resistive layer by ion implantation. In this way, it gets around the parasitic injection of electrons mentioned above and, at the same time, enhances the current gain of the HBT thus produced.
FIG. 1 shows the manufacturing method used by Yamahata et al. In the first place, a metal collector contact is deposited on the epitaxial structure. It is used as a mask for etching the collector layer (FIG. 1a). The structure is then implanted with oxygen ions through the base with an energy which is determined so as to render the extrinsic emitter regions (FIG. 1b) electrically isolating. A zinc diffusion makes it possible to re-establish a sufficient level of p+ doping of the base layer which was damaged during the ion implantation (FIG. 1c). The metal base contacts are then deposited. The base and emitter layers are then etched in order to deposit metal emitter contacts on an n+ doped sub-emitter. The component thus produced exhibits low base-collector capacitance and a heavily doped base.
Such a manufacturing method exhibits certain drawbacks. First of all, the base is severely damaged during the stage of oxygen-ion implantation. This is because, with the wafer being disoriented by 7° with respect to the direction of the implantation beam, it is therefore seen by the latter in a quasi-amorphous state. The number of crystalline defects generated in the base is therefore a maximum. The zinc diffusion makes it possible partly to mask this degradation, but does not make it possible to regain the initial conductivity of the base. Moreover, during stages of implantation and of diffusion, the flanks of the collector mesa have to be protected by a nitride which induces a lithography stage and a supplementary process stage. With this method, the surface area of the intrinsic active area is defined, therefore limited, by the size of the collector. It should be noted that, because of the high diffusion of the zinc, there exists a substantial risk of seeing short-circuits appear at the base-emitter junction, having a devastating impact on the reliability of the components.
The THOMSON-CSF Central Research Laboratory started to produce GaInP/GaAs heterojunction bipolar transistors (D-HBT) in collector-up technology, as described in the article by HENKEL et al., IEEE Electronics Letters, Vol. 33, No. 7, March 1997. The emitter region situated below the extrinsic base is, here again, converted into a highly resistive layer, but by an ion implantation which is optimized with a view to keeping the base at its initial conductivity.
FIG. 2 shows the manufacturing method used. A metal collector contact is first of all deposited on the epitaxial structure. It is used as a mask for etching the collector layer (FIG. 2a). The structure is then implanted with boron ions through the base, and at a low dose (FIG. 2b). The angle of implantation is 0° so as to minimize the collisions between the boron ions and the crystalline lattice of the base. The metal base contacts are then deposited. The base and emitter layers are then etched in order to deposit metal emitter contacts (FIG. 2c) on an n+ doped sub-emitter. These contacts then undergo annealing (416° C. for 10 mins, for example) allowing for the formation of an alloy at the metal/semiconductor interface. It is important to note that the resistivity of the base, which increases slightly during the ion-implantation stage, decreases and reverts, on completion of this annealing, to its initial value.
This manufacturing process, based on the different sensitivity of the conductivity of different semiconductor materials subjected to the same ion implantation, makes it possible, in a very effective way, to isolate the extrinsic emitter areas electrically while maintaining the conductivity of the base layer at a value close to its initial value. This latter property is, on the one hand, related to the fact that the implantation is done at lower dose. The number of crystalline defects generated in the base is therefore minimized. Moreover, the wafer is no longer disorientated with respect to the direction of the implantation beam (angle of implantation zero), the ions implanted are thus channeled into the crystalline network. The possibilities of a collision between an incident boron particle and the atoms and the electrons constituting the base material are then reduced. The same goes for the number of crystalline defects generated in the base. Moreover, the zinc-diffusion stage proposed by Yamahata et al. is then superfluous, bringing about simplification of the manufacturing method.
This particularly advantageous manufacturing method exhibits certain limitations, however. This is because, whereas the UHF performance of this type of component is particularly attractive (Fmax=115 GHz), the value of the static current gain obtained is low. In order to analyze this behavior, we have to recall the results of the work by HORIO et al., published in IEEE Transactions on Electron Devices, Vol. 42, No. 11, November 1995.
The work by HORIO et al. bears on emitter-up HBT devices produced with GaAlAs/GaAs materials. This work highlighted an accumulation of electrons in the extrinsic base regions in the case in which the emitter-up HBT features an extrinsic collector made perfectly isolating and a surface area of the base-collector junction slightly less than that of the emitter-base junction. From this accumulation there results, on the one hand, a degradation in the cut-off frequency of the current gain ft and, on the other hand, a recombination of the carriers in the base which will heavily penalize the static gain of the transistor. In the case of a structure which is similar but featuring a semi-isolating extrinsic collector (which corresponds to an extrinsic collector electrically isolated by ion implantation), the phenomenon of electron accumulation seems much more limited, and therefore the degradations in the current gain and in ft become much smaller. Moreover, Horio observes that the performance of the component is optimal when the surface area of the emitter-base junction is slightly less than that of the base-collector junction, and is so whatever the nature of the extrinsic collector (isolating or semi-isolating).
Unfortunately, the collector-up topology amounts to being placed in the most unfavorable of the preceding two cases. This is because, in this structure, the surface area of the collector at the base-collector junction defines the active area of the component. The extrinsic collector areas are therefore non-existent and can be modeled by a perfect insulant. In this configuration, if the surface area of the base-collector junction is less than that of the emitter-base junction, the phenomenon of electron accumulation in the extrinsic-base regions is particularly significant. The same goes for the emitter-up topology; the optimal performance is obtained when the surface area of the emitter-base junction is the smaller of the two. The production of high-performance collector-up components therefore requires perfect control of the techniques of implantation and of etching which will culminate in the definition of the surface areas of the two junctions.
In the case of heterojunction bipolar transistors in collector-up topology, the etching of the collector mesa is based on the selectivity of etching between the two materials constituting collector and base (the case of the D-HBT) or base and etching-stop layer (the case of the S-HBT). The metal collector contact is used as a mask for etching the collector. The surface area of this contact therefore defines that of the base-collector junction plus or minus the sub-etching (if any).
FIG. 3 shows the etching profile which is obtained according to the crystalline orientation for a collector made of GaInP (the case of the D-HBT). This profile is conventionally obtained by chemical etching (for example by the use of hydrochloric acid, diluted or otherwise). It will be noted that, depending on the crystalline orientation, a re-entrant or outgoing angle is observed. The example is taken for the case of a GaAs substrate (100) oriented according to the European/Japanese standard for indexing wafers. The shape indicated is obtained very simply with the condition that the layer of GaInP is sufficiently fine (of the order of 0.5 μm). It will be noted that the etching of the GaInP is blocked at the GaAs/GaInP interface, which makes manufacturing easier (see French patent No 2 697 945). The layer of GaAs thus fixes the lateral dimension of the device. Once the structure has been implanted with boron, the surface area of the emitter-base junction is defined by the shape of the isolating wells created in the extrinsic emitter area. As could be seen above, the metal collector contact serves as an implantation mask, but the shape of these wells will also depend on the profile of the flanks of the collector mesa.
Thus, for a D-HBT in which the collector spigot is oriented along the crystallographic direction <0 1 1>, the flanks of the collector mesa are re-entrant (FIG. 4a). If x is defined as the difference between the width of the extrinsic collector (defined by the etching) and that of the extrinsic emitter (defined by the shape of the isolating wells), x is then negative and on the order of −0.2 μm. The emitter-base junction therefore exhibits a surface area greater than that of the base-collector junction, and x is sufficiently large enough to entail a substantial degradation in the current gain and in ft.
If the collector electrode of the D-HBT is oriented along the crystallographic direction <0 1 −1>, the etching profile is then outgoing. The flanks of the collector mesa, which are not protected by the collector metalization, are then exposed to the ion implantation with boron. This gives rise to the appearance of isolating wells in the emitter 1, and also in the collector 2 (FIG. 4b). The width of the extrinsic collector is no longer defined by etching but by the shape of the collector-isolating wells. x is then negative, but small in absolute value. The degradation in the current gain and in f, is then less significant than in the preceding case, but is still present, however.
The etching of a collector made of GaAs (case of the S-HBT) is carried out in two operations: a reactive-ion etching (such as SiCl4) followed by a chemical etching (with citric acid, for example). This is because, in order not to damage the base material, advantage can be taken of the existence of the very wide selectivity of etching between a phosphorus-based layer and an arsenic-based layer. An etching-stop layer of shallow thickness is therefore added between the collector (n GaAs) and the base (p+ GaAs). Made for example from GaInP, it makes it possible to stop the etching of the collector made of GaAs. A chemical etching of the stop layer is then carried out using a solution which may be based, for example, on dilute hydrochloric acid. On completion of this sequence, the profile obtained does not depend on the crystalline orientation and exhibits an outgoing angle associated with a sub-etching at the interface with the ohmic contact (FIG. 4c). The width of the extrinsic collector is therefore defined by the etching flanks and x is, here again, negative but small in absolute value. The degradation in the current gain and in ft is substantially the same as in the preceding case.